The 3DS technology refers to 3 Dimensional Stacking of DRAM memory on the memory board to produce high-capacity memory modules.
This three-dimensional manufacturing technology was defined by JEDEC as a standard for memory modules under the term “3DS.”
In this process, 2, 4, or 8 DRAM DIE (DIE = individual silicon substrate chip) are stacked in a DRAM package and connected with vertical channels from DIE to DIE.
The connection is made internally through vertical TSV (Through-Silicon Vias) lines in this modern form of “stacking.”
The DRAM DIE stacks consist of a master DIE and one or more slave DIE.
The system’s memory controller interacts only with the master DIE, while the slave DIE are controlled autonomously by the master DIE.
This structure gives a 3DS memory physical ranks and logical ranks: A 128GB 3DS memory labeled “4H TSV 2S4Rx4” has 8 ranks (2 physical ranks x 4 logical ranks) on the memory module. This memory consists of 36 DRAM DIE stacks, each with 4 DIE stacked on top (=4H TSV).
Of the 4 DIE per DRAM DIE stack, only the master DIE is directly addressed by the memory controller. The 128GB 3DS memory module with 2S4Rx4 has 36 DRAM DIE stacks, resulting in 2 physical ranks (2 ranks = 36 master DIE with x4 structure = 2 ranks at 72 bits) but 8 logical ranks (36 DRAM DIE stacks with 4 DRAMs each with x4 structure = 8 ranks at 72 bits).
Due to the unique method of memory addressing, a 3DS-RDIMM or 3DS-LRDIMM cannot be used together with conventional RDIMM and LRDIMM memory without a 3DS structure on the same memory channel.
The 3DS technology is often just a bridging technology until the structures of DRAMs can be further reduced. This will enable the next doubling of memory capacity per DRAM (and thus the memory modules). With the new DRAM generation, the 3DS construction of the older DRAM will quickly be replaced.
Example: 64GB DDR4 3DS-RDIMM as 2S2Rx4 (2 physical ranks x 2 logical ranks = 4 logical ranks). Only the physical ranks are counted. For the system, the memory is therefore a 2Rx4 memory. Internally, 2 DRAMs of 2Gbit x 4 are interconnected via TSV lines.